Tamper evidence and tamper resistance

Tamper evidence is an external indication that someone has tried to compromise a device's physical security; tamper resistance makes such attempts difficult, costly or both; and tamper response is an automatic action, at minimum erasing plaintext keys, taken when tampering is detected S-1605 S-1600.

The US standard for cryptographic modules, FIPS 140-2, since superseded by FIPS 140-3, layers these properties S-1605:

• Level 2 requires evidence of tampering, such as tamper-evident coatings or seals, or pick-resistant locks on covers and doors S-1605.
• Level 3 adds detection and response circuitry that zeroizes plaintext secret and private keys when covers or doors are opened S-1605.
• Level 4 requires a complete envelope of protection intended to detect and respond to all unauthorized attempts at physical access S-1605.

These properties matter because the prover usually controls the hardware: Shavit notes that unlimited physical access could undermine a chip's attestation, and relies on inspections to find hardware attacks that damage chips in ways that are hard to hide S-0029. The flexHEG proposal houses its guarantee processor in a secure enclosure that provides physical tamper protection (Hardware-enabled guarantees (flexHEG) and guarantee processors) S-0035. One verification plan names tamper-evident enclosures among "promising future directions and existing methods" for physical security of AI computing infrastructure S-0067. Protecting verifier equipment in the prover's facility, such as network taps and recomputation servers, is the subject of tamper evidence for verifier devices. Seals can be defeated with simple methods: a 1996 Los Alamos study demonstrated low-tech defeats for each of the 94 passive and electronic seals it examined, with a mean defeat time of 4.3 minutes for one practised person S-1317.